1 features + - + - v ref sync oscillator error amp 1 error amp 2 latching pwm 2 latching pwm 1 v ref undervoltage lockout 5.0v ref v cc undervoltage lockout v cc v fb 1 comp 1 enable 2 v fb 2 comp 2 c t r t gnd pwr gnd sense 2 v out 2 sense 1 v out 1 oscillator has precise duty cycle limit and frequency control 500khz current mode operation automatic feed forward compensation separate latching pwms for cycle-by-cycle current limiting internally trimmed reference with undervoltage lockout switchable second output two high current totem pole outputs input undervoltage lockout with hysteresis 8.4v start up voltage threshold package options 16 lead so wide cs5661 high performance dual channel current mode controller with enable 1 sync 2 3 4 5 6 7 8 c t r t v fb 1 comp 1 sense 1 v out 1 gnd 16 15 14 13 12 11 10 9 v cc v ref enable 2 v fb 2 comp 2 sense 2 v out 2 pwr gnd cs5661 description the cs5661 is a high performance, fixed frequency, dual current mode controller specifically designed for off-line and dc to dc converter applications. it offers the designer a cost effective solution with minimal external components. this integrat- ed circuit features a unique oscilla- tor for precise duty cycle limit and frequency control, a temperature compensated reference, two high gain error amplifiers, two current sensing comparators, and two high current totem pole outputs ideally suited for driving power mosfets. v out 2 output is switchable via the enable 2 pin. also included are protective fea- tures consisting of input and refer- ence undervoltage lockouts, each with hysteresis, cycle-by-cycle cur- rent limiting, and a latch for single pulse metering of each output. the cs5661 is pin compatible with the mc34065l. block diagram june, 1999 - rev. 2 on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?600 fax: (401)885?786 n. american technical support: 800-282-9855 web site: www.cherry?emi.com
2 electrical characteristics: (v cc = 15v, r t = 8.2k ? , c t = 3.3nf, for typical values t a = 25?, for min/max values -40? < t a < 85?, unless otherwise stated. parameter test conditions min typ max unit absolute maximum ratings output current, source or sink (note 1) ........................................................................................ ..............................400ma output energy (capacitive load per cycle) ...................................................................................... .................................5.0 j current sense, enable and voltage .............................................................................................. ........................-0.3 to +5.5v feedback inputs sync input ?high state (voltage) .............................................................................................. ........................................5.5v ?low state (reverse current) .................................................................................................. .................-5.0ma error amp output sink current.................................................................................................. ....................................10ma storage temperature range ...................................................................................................... ..........................-65 to +150? operating junction temperature................................................................................................. ..................................+150? lead temperature soldering reflow (smd styles only) ......................................................................................60 sec. max above 183?, 230? peak esd capability (human body model) .............................................................................................. .....................................2kv cs5661 reference section reference output voltage, i out = 1.0ma, t j = 25? 4.9 5.0 5.1 v v ref line regulation 11v v cc 15v 2.0 20.0 mv load regulation 1.0ma i out 10ma 3.0 30.0 mv total output variation over 4.85 5.15 v line, load and temperature output short circuit current 30 100 ma oscillator and pwm sections total frequency variation 11v v cc 15v, t low t a t high 46.0 49.5 53.0 khz over line and temperature frequency change with 11v v cc 15v 0.2 1.0 % voltage duty cycle at each output maximum 46.0 49.5 52.0 % sync current high state v in = 2.4v 170 250 a low state v in = 0.8v 80 160 error amplifiers voltage feedback input v out = 2.5v 2.42 2.50 2.58 v input bias current v fb = 5.0v -0.1 -1.0 a open-loop voltage gain 2.0v v out 4.0v 65 100 db unity gain bandwidth t j = 25? (note 5) 0.7 1.0 mhz power supply rejection ratio v cc = 11v to 15v 60 90 db output current source v out = 3.0v, v fb = 2.3v -0.45 -1.00 ma sink v out = 1.2v, v fb = 2.7v 2.00 12.00 ma output voltage swing high state r l = 15k ? to ground, v fb = 2.3v 5.0 6.2 v low state r l = 15k ? to v ref , v fb = 2.7v 0.8 1.1 v
3 cs5661 parameter test conditions min typ max unit note 1: maximum package power dissipation limits must be observed. note 2: low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible: t low = -40? ; t high =+85? note 3: this parameter is measured at latch trip point with v fb =0v. note 4: comparator gain is defined as: av= note 5: these parameters are guaranteed by design but not 100% tested in production. ? v compensation ? v current sense current sense section current sense input (notes 3 and 4) 2.75 3.00 3.25 v/v voltage gain maximum current sense (note 3) 0.9 1.0 1.1 v input threshold input bias current -2.0 -30.0 a propagation delay current sense input to output (n ote 5) 150 300 ns output 2 enable pin enable pin voltage v high state output 2 enabled 3.5 v ref v low state output 2 disabled 0.0 1.5 v low state input current v il = 0v 100 250 400 a drive outputs output voltage low state i sink = 20ma 0.1 0.4 v i sink = 200ma 1.6 2.5 v high state i source = 20ma 13.0 13.5 v i source = 200ma 12.0 13.4 v output voltage with (v cc = 6.0v, i sink = 1.0ma) 0.1 1.1 v uvlo activated output voltage rise time (c l = 1.0nf) note 5 28 150 ns output voltage fall time (c l = 1.0nf) note 5 25 150 ns undervoltage lockout section start-up threshold 7.4 8.4 9.4 v minimum operating voltage after turn-on 6.8 7.8 8.8 v hysteresis 0.6 v total device start-up current v cc = 6v 0.6 1.0 ma operating current 20 25 ma electrical characteristics: (v cc = 15v, r t = 8.2k ? , c t = 3.3nf, for typical values t a = 25?, for min/max values -40? < t a < 85?, unless otherwise stated.
4 cs5661 package pin description package pin # pin symbol function typical performance characteristics 100pf 1.0nf 10k 30k 50k 100k 300k 500k 1.0m f osc oscillator frequency (hz) 4.0 6.0 8.0 10 12 14 16 r t timing resistor (k ? ) t a =25 c 2 .2 n f 3.3nf 5.0nf c t =10nf v cc = 15v 220pf 330pf 500pf 10k 30k 50k 100k 300k 500k 1.0m f osc oscillator frequency (hz) 38 40 42 44 46 48 50 maximum duty cycle (%) v cc = 15v r t = 4.0k ? to 16k ? c l = 15pf t a = 25 c max. output duty cycle vs. oscillator frequency timing resistor vs. oscillator frequency 10k 100k 1.0k 10k 100k 1.0m 10m f, frequency (hz) -20 0 20 40 60 80 100 a vol , open-loop voltage gain (db) v cc = 15v v o = 1.5v to 2.5v r l = 100k ? t a = 25 c gain phase 180 150 120 90 60 30 0 phase margin (degrees) 0 1.0 2.0 3.0 4.0 5.0 7.0 error amp output voltage (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 vth, current sense input threshhold (v) 6.0 v cc = 15v t a = 125 c t a = 25 c t a = -55 c current sense input threshold vs. error amp output voltage error amp open-loop gain & phase vs. frequency 16 lead so wide 1 sync a positive going pulse applied to this input will synchronize the oscillator. a dc voltage within the range of 2.4v to 5.5v will inhibit the oscillator. 2c t timing capacitor c t connects pin to ground setting oscillator frequency. 3r t resistor r t connects to ground setting the charge current for c t . its value must be between 4.0k ? and 16k ? . 4v fb 1 the inverting input of error amplifier 1. normally it is connect- ed to the switching power supply output. 5 comp 1 the output of error amplifier 1, for loop compensation. 6 sense 1 output 1 pulse by pulse current limit. 7v out 1 drives the power switch at output 1. 8 gnd logic ground 9 pwr gnd power ground. power device return is connected to this pin. 10 v out 2 drives the power switch at output 2. 11 sense 2 output 2 pulse by pulse current limit. 12 comp 2 output of error amplifier 2, for loop compensation. 13 v fb 2 inverting input of error amplifier 2. normally it is connected to the switching power supply output. 14 enable 2 output 2 disable. a logic low at this pin disables v out 2 . 15 v ref 5.0v reference output. it can source current in excess of 30ma. 16 v cc the positive supply of the ic. the minimum operating voltage after start-up is 8.8v.
5 the cs5661 is a high performance, fixed frequency, dual channel current mode pwm controller for off-line and dc to dc converter applications. each channel contains a high gain error amplifier, current sensing comparator, pulse width modulator latch, and totem pole output driv- er. the oscillator, reference, and undervoltage lockout cir- cuits are common to both channels. the oscillator has both precise frequency and duty cycle control. the oscillator frequency is programmed by the timing components r t and c t . capacitor c t is charged and discharged by an equal magnitude internal current source and sink that generates a symmetrical 50 percent duty cycle waveform at c t . the oscillator peak and valley thresholds are 3.5v and 1.6v respectively. the source/ sink current is controlled by resistor r t . for proper opera- tion over temperature range r t ? value should be between 4.0k ? to 16k ? . as c t charges and discharges, an internal blanking pulse is generated that alternately drives the inputs of the upper and lower nor gates high. this, in conjunction with a precise amount of delay time introduced into each chan- nel, produces well defined non-overlapping output duty cycles. output 2 is enabled while c t is charging, and output 1 is enabled during the discharge. even at 500khz, each output is capable of approximately 44% duty cycle, making this controller suitable for high frequency power conversion applications. in noise sensitive applications it may be necessary to syn- chronize the converter with an external system clock. this can be accomplished by applying an external clock signal. for reliable synchronization, the oscillator frequency should be set about 10% slower than the clock frequency. the rising edge of the clock signal applied to sync, termi- nates the charging of c t and v out 2 conduction. by tailor- ing the clock waveform symmetry, accurate duty cycle clamping of either output can be achieved. each channel contains a fully-compensated error amplifier with access to the output and inverting input. the amplifi- er features a typical dc voltage gain of 100 db, and a unity gain bandwidth of 1.0 mhz with 71 degrees of phase mar- gin. the non-inverting input is internally biased at 2.5v. the converter output voltage is typically divided down and monitored by the inverting input through a resistor divider. the maximum input bias current is -1.0 a which will cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider resistance. its output voltage is offset by two diode drops ( 1.4v) and divided by three before it connects to the inverting input of the current sense comparator. this guarantees that both operating description cs5661 typical performance characteristics: continued 0 20 40 60 80 100 120 i ref , reference source current (ma) -24 -20 -16 -12 -8.0 -4.0 0 ? v ref , reference voltage (mv) v cc = 15v t a = ?5 c t a = 125 c t a = 25 c -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) i sc , reference short circuit current (ma) 120 100 80 60 reference short circuit current vs. temperature reference voltage change vs. source current source saturation (load to ground) v cc =15v 80 s pulsed load 120hz rate t a =25 c t a = ?5 c t a = ?5 c t a =25 c sink saturation (load to v cc ) gnd 0 200 400 600 800 output load current (ma) v sat , output saturation voltage (v) v cc 0 -1.0 -2.0 2.0 1.0 0 8.4 v cc, supply voltage (v) - cs-5661 0 8.0 16 24 32 r t =8.2k ? c t =3.3nf v fb 1, 2=0v current sense 1, 2=0v t a =25 c i cc, supply current (ma) supply current vs. supply voltage output saturation voltage vs. load current oscillator error amplifier
6 outputs are disabled when the error amplifier output is at its lowest state (v out(low) ). this occurs when the power supply is operating at light or no-load conditions, or at the beginning of a soft-start interval. the minimum allowable error amplifier feedback resis- tance is limited by the amplifier? source current capability (0.5 ma) and the output voltage (v out(high) ) required to reach the current sense comparator 1.0v clamp level with the error amplifier inverting input at ground. this condi- tion happens during initial system start up or when the sensed output is shorted: r f(min) = 8.8k ? the cs5661 operates as current mode controller. output switch conduction is initiated by the oscillator and termi- nated when the peak inductor current reaches the thresh- old level established by the error amplifier output. the error signal controls the peak inductor current on a cycle- by-cycle basis. the current sense comparator-pwm latch combination ensures that only a single pulse appears at the output during any given oscillator cycle. the current is converted to a voltage by connecting sense resistor r sense in series with the source of output switch q1 and ground. this voltage is monitored via the sense 1,2 pins and com- pared to a voltage derived from the error amp output. the peak current under normal operating conditions is con- trolled by the voltage at comp where: i pk = abnormal operating conditions occur when the power supply output is overloaded or if output voltage is too high. under these conditions, the current sense comparator threshold will be internally clamped to 1.0v. therefore the maximum peak switch current is: i pk(max) = erratic operation due to noise pickup can result if there is an excessive reduction of the i pk(max) clamp voltage. a narrow spike on the leading edge of the current wave- form can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. the addition of an rc filter on the current sense input reduces this spike to an acceptable level. two undervoltage lockout comparators have been incor- porated to guarantee that the ic is fully functional before the output stages are enabled. v cc and the reference out- put v ref are monitored by separate comparators. each comparator has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. the v cc comparator upper and lower thresholds are 8.4v and 7.8v, respectively. the v ref comparator disables the out- puts until the internal circuitry is functional. this compara- tor has upper and lower thresholds of 3.6v and 3.4v. the guaranteed minimum operating voltage after turn-on is 8.8v. each channel contains a single totem-pole output stage specifically designed for driving a power mosfet. the outputs have up to 400ma peak current capability and have a typical rise and fall time of 28ns with a 1.0nf load. internal circuitry has been added to keep the outputs in active pull-down mode whenever undervoltage lockout is active. an external pull-down resistor is not needed. cross-conduction current in the totem-pole output stage has been minimized for high speed operation. the average added power due to cross-conduction with v cc =15v is only 60mw at 500khz. although the outputs were optimized for mosfet?, they can easily supply the negative base current required by bipolar npn transistors for enhanced turn-off. because the outputs do not contain internal current limiting circuitry, an external series resistor may be required to prevent the peak output current from exceeding the 400ma maxi- mum rating. the sink saturation voltage (v ol ) is less than 0.4v at 20ma. a separate power ground pin is provided and will signifi- cantly reduce the level of switching transient noise imposed on the control circuitry. this input is used to switch v out 2 . v out 1 can be used to control circuitry that runs continuously; e.g. volatile mem- ory, the system clock, or a remote controlled receiver. the v out 2 output can control the high power circuitry that can be turned off when not needed. the 5.0v bandgap reference is trimmed to 2.0% tolerance. the reference has short circuit protection and is capable of sourcing 30ma for powering any additional external cir- cuitry. high frequency circuit layout techniques are imperative to prevent pulse-width jitter. this is usually caused by exces- sive noise pick-up imposed on the current sense or voltage feed-back inputs. noise immunity can be improved by lowering circuit impedances at these points. the printed circuit board layout should contain a ground plane with low current signal and high current switch and output grounds returning on separate paths back to the input fil- design considerations voltage reference enable 2 outputs and power ground 1.0v r sense v comp ?1.4v 3r sense current sense comparator and pwm latch (3 x 1.0v) + 1.4v 0.5ma operating description: continued cs5661 undervoltage lockout
7 ter capacitor. ceramic bypass capacitors (0.1 f) connected directly to v cc and v ref may be required to improve noise filtering. this provides a low impedance path for filtering the high frequency noise. all high current loops should be kept as short as possible using heavy copper runs. the error amp compensation circuitry and the converter out- put voltage-divider should be located close to the ic and as far as possible from the power switch and other noise generating components. operating description: continued cs5661 sync capacitor c t latch 1 ?et?input comp 1 sense 1 v out 1 latch 1 ?eset?input enable 2 latch 2 ?et?input comp 2 sense 2 latch 2 ?eset?input v out 2 0v timing diagram + - + + + + - r t c t v fb 1 reference regulator v ref uvlo 3.4v 8.4v 2.5v r r 20k ? v ref sync 1ma 2r 1.0v 250 a r 2r error amp 2 comp 1 enable 2 v fb 2 comp 2 gnd pwr gnd r 1.0v current sense comparator 2 current sense comparator 1 r s r s r pwm latch 2 pwm latch 1 v cc v in v out1 v out2 sense 1 q1 q2 r sense 1 sense 2 r sense 2 - + - error amp 1 v out1 v out2 c out2 c out1 5.0v q oscillator internal bias c f1 + l 1 d 1 l 2 d 2 + + c f2 r fb 1 r fb 2 r fb 3 r fb 4 v out 2 v out1 dual boost regulator v cc uvlo + q + - + - + - + - 1ma typical application diagram
part number description cs5661edw16 16l so wide cs5661edwr16 16l so wide (tape & reel) 8 thermal data 16 lead so r jc typ 23 c/w r ja typ 105 ?/w d lead count metric english max min max min 16l so 10.50 10.10 .413 .398 package specification package dimensions in mm (inches) ordering information package thermal data cs5661 surface mount wide body (dw); 300 mil wide 1.27 (.050) bsc 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) d 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) ref: jedec ms-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 2.35 (.093) 0.30 (.012) 0.10 (.004) on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ?semiconductor components industries, llc, 2000
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